True LRU based on true recency.
TLRU and TRC are abbreviations for TrueLRU (spica/tlru).
The source code is maintained on the next source repository.
https://github.com/falsandtru/spica
- True LRU
LRU and Clock are significantly low performance due to their wrong algorithm based on false recency. True recency outperforms false recency.
There are three kinds of recency relationships between entries, used and used, used and unused, and unused and unused. However, LRU and Clock violate some recency. True LRU outperforms LRU and Clock by observing all recency.
The fundamental error of LRU is that new entries are considered most recently used. In fact, they have never been used in the cache. Therefore, new entries must to be added after the entries actually used.
Sequence: 1, 2, 3, 3, 2, 4
LRU
MRU |4 2 3 1| LRU
Hit |0 1 1 0|
^ Violation of the recency between used and unused.
Clock
N-1 |4 3 2 1| 0
Hit |0 1 1 0|
^ Violation of the recency between used and used.
True LRU
MRU |2 3 4 1| LRU
Hit |1 1 0 0|
^ ^ ^ Ideal recency.
As with reuse distance, there is a difference between unused and used in recency, whether infinite or finite, and there are various possible ways to bridge the difference.
The large improvement from LRU in True LRU indicates that the majority of the improvements in all algorithms are due to the accidental eviction of unused entries, which are confused and misinterpreted as unique improvements, and that the improvements due to the uniqueness of each algorithm are small or minor. Taking True LRU as the true baseline instead of LRU, the other algorithms have not achieve very attractive performance, especially in general versatility.
Incidentally, Clock is known as an approximation algorithm for LRU, but since LRU and Clock are thus algorithms based on a different kind of recency, Clock is actually not an approximation algorithm for LRU but a completely different recency-based algorithm based on a different kind of recency.
Some different cache algorithms require extra memory space to retain evicted keys. Linear time complexity indicates the existence of batch processing. Note that admission algorithm doesn't work without eviction algorithm.
| Algorithm | Type | Time complexity (Worst case) |
Space complexity (Extra) |
Key size | Data structures |
|---|---|---|---|---|---|
| LRU | Evict | Constant | Constant | 1x | 1 list |
| SLRU | Evict | Constant | Constant | 1x | 1 list |
| TLRU | Evict | Constant | Constant | 1x | 1 list |
| DWC | Evict | Constant | Constant | 1x | 2 lists |
| ARC | Evict | Constant | Linear | 2x | 4 lists |
| LIRS | Evict | Linear | Linear | 3-2,500x | 2 lists |
| W-TinyLFU | Admit | Linear | Linear |
~1-10x (8bit * 10N * 4) |
1 list 4 arrays |
https://github.com/ben-manes/caffeine/wiki/Efficiency
https://github.com/zhongch4g/LIRS2/blob/master/src/replace_lirs_base.cc
A pointer is 8 bytes, bool and int8 are each 1 byte in C.
Memoize, etc.
| Algorithm | Entry overhead | Key size | Total per entry | Attenuation coefficient |
|---|---|---|---|---|
| LRU | 16 bytes | 1x | 32 bytes | 100.00% |
| SLRU | 16 bytes | 1x | 32 bytes | 100.00% |
| TLRU | 16 bytes | 1x | 32 bytes | 100.00% |
| DWC | 17 bytes | 1x | 33 bytes | 96.96% |
| ARC | 17 bytes | 2x | 58 bytes | 55.17% |
| LIRS | 33 bytes | 3x | 131 bytes | 24.42% |
| LIRS | 33 bytes | 10x | 418 bytes | 7.65% |
| W-TinyLFU | 56 bytes | 1x | 72 bytes | 44.44% |
In-memory KVS, etc.
| Algorithm | Entry overhead | Key size | Total per entry | Attenuation coefficient |
|---|---|---|---|---|
| LRU | 16 bytes | 1x | 56 bytes | 100.00% |
| SLRU | 16 bytes | 1x | 56 bytes | 100.00% |
| TLRU | 16 bytes | 1x | 56 bytes | 100.00% |
| DWC | 17 bytes | 1x | 57 bytes | 98.24% |
| ARC | 17 bytes | 2x | 88 bytes | 63.63% |
| LIRS | 33 bytes | 3x | 203 bytes | 27.58% |
| LIRS | 33 bytes | 10x | 658 bytes | 8.51% |
| W-TinyLFU | 56 bytes | 1x | 96 bytes | 58.33% |
DNS cache server, etc.
| Algorithm | Entry overhead | Key size | Total per entry | Attenuation coefficient |
|---|---|---|---|---|
| LRU | 16 bytes | 1x | 544 bytes | 100.00% |
| SLRU | 16 bytes | 1x | 544 bytes | 100.00% |
| TLRU | 16 bytes | 1x | 544 bytes | 100.00% |
| DWC | 17 bytes | 1x | 545 bytes | 99.81% |
| ARC | 17 bytes | 2x | 578 bytes | 94.11% |
| LIRS | 33 bytes | 3x | 659 bytes | 82.54% |
| LIRS | 33 bytes | 10x | 1,002 bytes | 54.29% |
| W-TinyLFU | 56 bytes | 1x | 584 bytes | 93.15% |
LIRS's burst resistance means the resistance to continuous cache misses for the last LIR entry or the HIR entries. TLRU's loop resistance is limited to initial only.
| Algorithm | Type | Scan | Loop | Burst |
|---|---|---|---|---|
| LRU | Evict | ✓ | ||
| SLRU | Evict | ✓ | ✓ | |
| TLRU | Evict | ✓ | ✓ | ✓ |
| DWC | Evict | ✓ | ✓ | ✓ |
| ARC | Evict | ✓ | ✓ | |
| LIRS | Evict | ✓ | ✓ | |
| W-TinyLFU | Admit | ✓ | ✓ | ✓ |
DWC automatically adjusts the history size according to the loop size.
| Algorithm | Method | Duration | Layout | History size | Resistance | Efficiency |
|---|---|---|---|---|---|---|
| TLRU | Eventual | Initial | Inner | 100% | > 10x | > 1,000% |
| DWC | Statistics | Permanent | Inner | 8% | 4x | 5,000% |
| DWC | Statistics | Permanent | Inner | 14% | 10x | 7,142% |
| DWC | Statistics | Permanent | Inner | 100% | 96x | 9,600% |
| LIRS | Log | Permanent | Outer | 300-250,000% | 3-2,500x | 100% |
| W-TinyLFU | Hash | Permanent | Outer | 500% | 4x | 80% |
Note that another cache algorithm sometimes changes the parameter values per workload to get a favorite result as the paper of TinyLFU has changed the window size of W-TinyLFU.
- DWC's results are measured by the same default parameter values.
- Other results are measured by the simulator in Caffeine.
- Set the datasets to
./benchmark/trace(See./benchmark/ratio.ts). - Run
npm i. - Run
npm run bench. - Click the DEBUG button to open a debug tab.
- Close the previous tab.
- Press F12 key to open devtools.
- Select the console tab.
W-TinyLFU > (LIRS), DWC > TLRU > ARC > SLRU > LRU
WS1 1,000,000
LRU hit ratio 2.95%
SLRU hit ratio 6.96%
TLRU hit ratio 8.09%
TLRU - LRU hit ratio delta 5.14%
TLRU - SLRU hit ratio delta 1.12%
WS1 2,000,000
LRU hit ratio 6.08%
SLRU hit ratio 12.67%
TLRU hit ratio 18.03%
TLRU - LRU hit ratio delta 11.94%
TLRU - SLRU hit ratio delta 5.35%
WS1 3,000,000
LRU hit ratio 9.63%
SLRU hit ratio 17.69%
TLRU hit ratio 26.92%
TLRU - LRU hit ratio delta 17.29%
TLRU - SLRU hit ratio delta 9.22%
WS1 4,000,000
LRU hit ratio 21.59%
SLRU hit ratio 27.09%
TLRU hit ratio 35.88%
TLRU - LRU hit ratio delta 14.28%
TLRU - SLRU hit ratio delta 8.78%
WS1 5,000,000
LRU hit ratio 33.91%
SLRU hit ratio 37.88%
TLRU hit ratio 44.19%
TLRU - LRU hit ratio delta 10.28%
TLRU - SLRU hit ratio delta 6.31%
WS1 6,000,000
LRU hit ratio 45.74%
SLRU hit ratio 48.43%
TLRU hit ratio 51.66%
TLRU - LRU hit ratio delta 5.92%
TLRU - SLRU hit ratio delta 3.22%
WS1 7,000,000
LRU hit ratio 54.89%
SLRU hit ratio 56.76%
TLRU hit ratio 57.70%
TLRU - LRU hit ratio delta 2.81%
TLRU - SLRU hit ratio delta 0.93%
WS1 8,000,000
LRU hit ratio 61.40%
SLRU hit ratio 62.12%
TLRU hit ratio 62.46%
TLRU - LRU hit ratio delta 1.06%
TLRU - SLRU hit ratio delta 0.34%
W-TinyLFU > (LIRS), DWC > TLRU, SLRU > ARC > LRU
WS2 1,000,000
LRU hit ratio 2.91%
SLRU hit ratio 12.31%
TLRU hit ratio 9.28%
TLRU - LRU hit ratio delta 6.37%
TLRU - SLRU hit ratio delta -3.03%
WS2 2,000,000
LRU hit ratio 6.19%
SLRU hit ratio 21.40%
TLRU hit ratio 19.86%
TLRU - LRU hit ratio delta 13.67%
TLRU - SLRU hit ratio delta -1.54%
WS2 3,000,000
LRU hit ratio 10.09%
SLRU hit ratio 28.48%
TLRU hit ratio 30.05%
TLRU - LRU hit ratio delta 19.95%
TLRU - SLRU hit ratio delta 1.57%
WS2 4,000,000
LRU hit ratio 23.45%
SLRU hit ratio 37.81%
TLRU hit ratio 40.41%
TLRU - LRU hit ratio delta 16.95%
TLRU - SLRU hit ratio delta 2.59%
WS2 5,000,000
LRU hit ratio 37.94%
SLRU hit ratio 48.89%
TLRU hit ratio 50.39%
TLRU - LRU hit ratio delta 12.45%
TLRU - SLRU hit ratio delta 1.50%
WS2 6,000,000
LRU hit ratio 51.69%
SLRU hit ratio 59.29%
TLRU hit ratio 60.05%
TLRU - LRU hit ratio delta 8.36%
TLRU - SLRU hit ratio delta 0.76%
WS2 7,000,000
LRU hit ratio 63.81%
SLRU hit ratio 69.45%
TLRU hit ratio 69.29%
TLRU - LRU hit ratio delta 5.48%
TLRU - SLRU hit ratio delta -0.15%
WS2 8,000,000
LRU hit ratio 73.11%
SLRU hit ratio 76.65%
TLRU hit ratio 76.33%
TLRU - LRU hit ratio delta 3.21%
TLRU - SLRU hit ratio delta -0.32%
ARC > SLRU, TLRU > (LIRS), DWC > LRU > W-TinyLFU
F1 2,500
LRU hit ratio 27.74%
SLRU hit ratio 28.32%
TLRU hit ratio 27.48%
TLRU - LRU hit ratio delta -0.25%
TLRU - SLRU hit ratio delta -0.83%
F1 5,000
LRU hit ratio 30.55%
SLRU hit ratio 32.18%
TLRU hit ratio 31.52%
TLRU - LRU hit ratio delta 0.96%
TLRU - SLRU hit ratio delta -0.66%
F1 7,500
LRU hit ratio 32.18%
SLRU hit ratio 34.48%
TLRU hit ratio 34.04%
TLRU - LRU hit ratio delta 1.86%
TLRU - SLRU hit ratio delta -0.43%
F1 10,000
LRU hit ratio 33.27%
SLRU hit ratio 35.98%
TLRU hit ratio 35.57%
TLRU - LRU hit ratio delta 2.29%
TLRU - SLRU hit ratio delta -0.41%
F1 12,500
LRU hit ratio 34.19%
SLRU hit ratio 37.09%
TLRU hit ratio 36.72%
TLRU - LRU hit ratio delta 2.53%
TLRU - SLRU hit ratio delta -0.36%
F1 15,000
LRU hit ratio 34.97%
SLRU hit ratio 37.79%
TLRU hit ratio 37.60%
TLRU - LRU hit ratio delta 2.63%
TLRU - SLRU hit ratio delta -0.18%
F1 17,500
LRU hit ratio 35.62%
SLRU hit ratio 38.45%
TLRU hit ratio 38.32%
TLRU - LRU hit ratio delta 2.70%
TLRU - SLRU hit ratio delta -0.12%
F1 20,000
LRU hit ratio 36.17%
SLRU hit ratio 39.01%
TLRU hit ratio 38.82%
TLRU - LRU hit ratio delta 2.65%
TLRU - SLRU hit ratio delta -0.18%
W-TinyLFU > DWC > TLRU, (LIRS) > SLRU > ARC > LRU
DS1 1,000,000
LRU hit ratio 3.08%
SLRU hit ratio 6.12%
TLRU hit ratio 10.47%
TLRU - LRU hit ratio delta 7.39%
TLRU - SLRU hit ratio delta 4.35%
DS1 2,000,000
LRU hit ratio 10.74%
SLRU hit ratio 23.31%
TLRU hit ratio 22.78%
TLRU - LRU hit ratio delta 12.03%
TLRU - SLRU hit ratio delta -0.52%
DS1 3,000,000
LRU hit ratio 18.59%
SLRU hit ratio 36.78%
TLRU hit ratio 34.45%
TLRU - LRU hit ratio delta 15.86%
TLRU - SLRU hit ratio delta -2.33%
DS1 4,000,000
LRU hit ratio 20.24%
SLRU hit ratio 39.07%
TLRU hit ratio 39.68%
TLRU - LRU hit ratio delta 19.44%
TLRU - SLRU hit ratio delta 0.61%
DS1 5,000,000
LRU hit ratio 21.03%
SLRU hit ratio 40.66%
TLRU hit ratio 46.69%
TLRU - LRU hit ratio delta 25.66%
TLRU - SLRU hit ratio delta 6.03%
DS1 6,000,000
LRU hit ratio 33.95%
SLRU hit ratio 49.80%
TLRU hit ratio 53.64%
TLRU - LRU hit ratio delta 19.68%
TLRU - SLRU hit ratio delta 3.83%
DS1 7,000,000
LRU hit ratio 38.89%
SLRU hit ratio 56.62%
TLRU hit ratio 61.28%
TLRU - LRU hit ratio delta 22.38%
TLRU - SLRU hit ratio delta 4.65%
DS1 8,000,000
LRU hit ratio 43.03%
SLRU hit ratio 57.56%
TLRU hit ratio 68.93%
TLRU - LRU hit ratio delta 25.90%
TLRU - SLRU hit ratio delta 11.36%
W-TinyLFU > (LIRS), DWC > TLRU, SLRU, ARC > LRU
S3 100,000
LRU hit ratio 2.32%
SLRU hit ratio 9.91%
TLRU hit ratio 6.99%
TLRU - LRU hit ratio delta 4.66%
TLRU - SLRU hit ratio delta -2.91%
S3 200,000
LRU hit ratio 4.63%
SLRU hit ratio 17.77%
TLRU hit ratio 15.49%
TLRU - LRU hit ratio delta 10.85%
TLRU - SLRU hit ratio delta -2.28%
S3 300,000
LRU hit ratio 7.58%
SLRU hit ratio 23.92%
TLRU hit ratio 23.85%
TLRU - LRU hit ratio delta 16.26%
TLRU - SLRU hit ratio delta -0.07%
S3 400,000
LRU hit ratio 12.03%
SLRU hit ratio 29.36%
TLRU hit ratio 31.94%
TLRU - LRU hit ratio delta 19.90%
TLRU - SLRU hit ratio delta 2.58%
S3 500,000
LRU hit ratio 22.76%
SLRU hit ratio 37.49%
TLRU hit ratio 40.35%
TLRU - LRU hit ratio delta 17.58%
TLRU - SLRU hit ratio delta 2.85%
S3 600,000
LRU hit ratio 34.63%
SLRU hit ratio 46.14%
TLRU hit ratio 48.40%
TLRU - LRU hit ratio delta 13.77%
TLRU - SLRU hit ratio delta 2.25%
S3 700,000
LRU hit ratio 46.04%
SLRU hit ratio 54.93%
TLRU hit ratio 55.86%
TLRU - LRU hit ratio delta 9.82%
TLRU - SLRU hit ratio delta 0.93%
S3 800,000
LRU hit ratio 56.59%
SLRU hit ratio 63.83%
TLRU hit ratio 63.88%
TLRU - LRU hit ratio delta 7.28%
TLRU - SLRU hit ratio delta 0.05%
ARC > DWC > SLRU, TLRU > W-TinyLFU > (LIRS) > LRU
OLTP 250
LRU hit ratio 16.47%
SLRU hit ratio 15.67%
TLRU hit ratio 17.06%
TLRU - LRU hit ratio delta 0.59%
TLRU - SLRU hit ratio delta 1.39%
OLTP 500
LRU hit ratio 23.44%
SLRU hit ratio 28.51%
TLRU hit ratio 27.86%
TLRU - LRU hit ratio delta 4.41%
TLRU - SLRU hit ratio delta -0.65%
OLTP 750
LRU hit ratio 28.28%
SLRU hit ratio 33.89%
TLRU hit ratio 33.11%
TLRU - LRU hit ratio delta 4.83%
TLRU - SLRU hit ratio delta -0.77%
OLTP 1,000
LRU hit ratio 32.83%
SLRU hit ratio 37.52%
TLRU hit ratio 36.53%
TLRU - LRU hit ratio delta 3.69%
TLRU - SLRU hit ratio delta -0.98%
OLTP 1,250
LRU hit ratio 36.20%
SLRU hit ratio 39.88%
TLRU hit ratio 38.88%
TLRU - LRU hit ratio delta 2.67%
TLRU - SLRU hit ratio delta -0.99%
OLTP 1,500
LRU hit ratio 38.69%
SLRU hit ratio 41.77%
TLRU hit ratio 40.79%
TLRU - LRU hit ratio delta 2.09%
TLRU - SLRU hit ratio delta -0.97%
OLTP 1,750
LRU hit ratio 40.78%
SLRU hit ratio 43.22%
TLRU hit ratio 42.36%
TLRU - LRU hit ratio delta 1.57%
TLRU - SLRU hit ratio delta -0.85%
OLTP 2,000
LRU hit ratio 42.46%
SLRU hit ratio 44.45%
TLRU hit ratio 43.65%
TLRU - LRU hit ratio delta 1.18%
TLRU - SLRU hit ratio delta -0.79%
W-TinyLFU, (LIRS) > DWC > TLRU >> SLRU > ARC > LRU
GLI 250
LRU hit ratio 0.93%
SLRU hit ratio 1.39%
TLRU hit ratio 10.62%
TLRU - LRU hit ratio delta 9.69%
TLRU - SLRU hit ratio delta 9.22%
GLI 500
LRU hit ratio 0.96%
SLRU hit ratio 1.39%
TLRU hit ratio 25.03%
TLRU - LRU hit ratio delta 24.06%
TLRU - SLRU hit ratio delta 23.63%
GLI 750
LRU hit ratio 1.16%
SLRU hit ratio 1.42%
TLRU hit ratio 37.28%
TLRU - LRU hit ratio delta 36.12%
TLRU - SLRU hit ratio delta 35.85%
GLI 1,000
LRU hit ratio 11.22%
SLRU hit ratio 31.34%
TLRU hit ratio 47.17%
TLRU - LRU hit ratio delta 35.95%
TLRU - SLRU hit ratio delta 15.82%
GLI 1,250
LRU hit ratio 21.25%
SLRU hit ratio 41.32%
TLRU hit ratio 52.04%
TLRU - LRU hit ratio delta 30.78%
TLRU - SLRU hit ratio delta 10.72%
GLI 1,500
LRU hit ratio 36.56%
SLRU hit ratio 51.86%
TLRU hit ratio 53.00%
TLRU - LRU hit ratio delta 16.43%
TLRU - SLRU hit ratio delta 1.14%
GLI 1,750
LRU hit ratio 45.04%
SLRU hit ratio 55.06%
TLRU hit ratio 55.88%
TLRU - LRU hit ratio delta 10.83%
TLRU - SLRU hit ratio delta 0.81%
GLI 2,000
LRU hit ratio 57.41%
SLRU hit ratio 57.41%
TLRU hit ratio 57.96%
TLRU - LRU hit ratio delta 0.54%
TLRU - SLRU hit ratio delta 0.54%
- Clock: spica/clock
- ILRU: lru-cache (https://www.npmjs.com/package/lru-cache)
- LRU: spica/lru
- TRC-C: spica/tlru (spica/tlru.clock)
- TRC-L: spica/tlru.lru
- DWC: spica/cache
https://github.com/falsandtru/spica/blob/master/benchmark/cache.ts
OS: Linux 6.2 Ubuntu 22.04.4 LTS 22.04.4 LTS (Jammy Jellyfish)
CPU: (4) x64 AMD EPYC 7763 64-Core Processor
Memory: 14.61 GB / 15.61 GB
Container: Yes
'Clock new x 1,718,249 ops/sec ±2.88% (115 runs sampled)'
'ILRU new x 17,988 ops/sec ±0.63% (119 runs sampled)'
'LRU new x 27,226,331 ops/sec ±1.17% (120 runs sampled)'
'TRC-C new x 25,876,900 ops/sec ±1.21% (120 runs sampled)'
'TRC-L new x 25,833,554 ops/sec ±1.22% (121 runs sampled)'
'DWC new x 8,576,715 ops/sec ±0.40% (122 runs sampled)'
'Clock simulation 100 10% x 10,013,697 ops/sec ±0.64% (123 runs sampled)'
'ILRU simulation 100 10% x 8,635,492 ops/sec ±0.61% (122 runs sampled)'
'LRU simulation 100 10% x 10,504,423 ops/sec ±0.93% (121 runs sampled)'
'TRC-C simulation 100 10% x 10,286,201 ops/sec ±0.83% (121 runs sampled)'
'TRC-L simulation 100 10% x 9,138,453 ops/sec ±0.87% (121 runs sampled)'
'DWC simulation 100 10% x 6,526,717 ops/sec ±0.30% (123 runs sampled)'
'Clock simulation 1,000 10% x 10,016,720 ops/sec ±0.37% (122 runs sampled)'
'ILRU simulation 1,000 10% x 7,865,319 ops/sec ±0.71% (121 runs sampled)'
'LRU simulation 1,000 10% x 10,125,647 ops/sec ±0.40% (123 runs sampled)'
'TRC-C simulation 1,000 10% x 9,527,825 ops/sec ±0.97% (120 runs sampled)'
'TRC-L simulation 1,000 10% x 8,363,899 ops/sec ±0.91% (120 runs sampled)'
'DWC simulation 1,000 10% x 6,873,911 ops/sec ±0.21% (123 runs sampled)'
'Clock simulation 10,000 10% x 8,913,804 ops/sec ±0.41% (122 runs sampled)'
'ILRU simulation 10,000 10% x 6,738,489 ops/sec ±0.33% (116 runs sampled)'
'LRU simulation 10,000 10% x 8,478,551 ops/sec ±0.68% (123 runs sampled)'
'TRC-C simulation 10,000 10% x 8,255,806 ops/sec ±0.54% (123 runs sampled)'
'TRC-L simulation 10,000 10% x 7,290,336 ops/sec ±0.66% (120 runs sampled)'
'DWC simulation 10,000 10% x 5,919,884 ops/sec ±0.28% (122 runs sampled)'
'Clock simulation 100,000 10% x 5,914,679 ops/sec ±1.76% (118 runs sampled)'
'ILRU simulation 100,000 10% x 3,570,629 ops/sec ±1.54% (116 runs sampled)'
'LRU simulation 100,000 10% x 5,724,682 ops/sec ±2.09% (118 runs sampled)'
'TRC-C simulation 100,000 10% x 6,105,347 ops/sec ±2.17% (116 runs sampled)'
'TRC-L simulation 100,000 10% x 5,421,814 ops/sec ±2.06% (116 runs sampled)'
'DWC simulation 100,000 10% x 4,446,710 ops/sec ±1.89% (116 runs sampled)'
'Clock simulation 1,000,000 10% x 2,836,324 ops/sec ±3.44% (106 runs sampled)'
'ILRU simulation 1,000,000 10% x 1,602,371 ops/sec ±2.70% (107 runs sampled)'
'LRU simulation 1,000,000 10% x 2,355,509 ops/sec ±3.30% (106 runs sampled)'
'TRC-C simulation 1,000,000 10% x 2,419,422 ops/sec ±2.85% (103 runs sampled)'
'TRC-L simulation 1,000,000 10% x 2,201,640 ops/sec ±3.05% (105 runs sampled)'
'DWC simulation 1,000,000 10% x 2,823,768 ops/sec ±4.18% (105 runs sampled)'
'Clock simulation 100 50% x 11,476,275 ops/sec ±0.45% (122 runs sampled)'
'ILRU simulation 100 50% x 10,695,622 ops/sec ±0.41% (122 runs sampled)'
'LRU simulation 100 50% x 12,423,614 ops/sec ±0.48% (122 runs sampled)'
'TRC-C simulation 100 50% x 11,687,869 ops/sec ±0.41% (122 runs sampled)'
'TRC-L simulation 100 50% x 11,121,712 ops/sec ±0.58% (122 runs sampled)'
'DWC simulation 100 50% x 6,432,098 ops/sec ±0.28% (124 runs sampled)'
'Clock simulation 1,000 50% x 11,278,805 ops/sec ±0.56% (123 runs sampled)'
'ILRU simulation 1,000 50% x 9,798,605 ops/sec ±0.34% (122 runs sampled)'
'LRU simulation 1,000 50% x 11,347,196 ops/sec ±0.40% (122 runs sampled)'
'TRC-C simulation 1,000 50% x 10,917,028 ops/sec ±0.28% (123 runs sampled)'
'TRC-L simulation 1,000 50% x 10,455,280 ops/sec ±0.39% (123 runs sampled)'
'DWC simulation 1,000 50% x 6,215,658 ops/sec ±0.30% (123 runs sampled)'
'Clock simulation 10,000 50% x 10,044,259 ops/sec ±0.40% (122 runs sampled)'
'ILRU simulation 10,000 50% x 8,118,211 ops/sec ±0.35% (123 runs sampled)'
'LRU simulation 10,000 50% x 9,107,620 ops/sec ±1.14% (122 runs sampled)'
'TRC-C simulation 10,000 50% x 8,214,162 ops/sec ±0.67% (120 runs sampled)'
'TRC-L simulation 10,000 50% x 7,801,660 ops/sec ±1.41% (121 runs sampled)'
'DWC simulation 10,000 50% x 4,915,591 ops/sec ±0.60% (123 runs sampled)'
'Clock simulation 100,000 50% x 6,815,193 ops/sec ±1.40% (118 runs sampled)'
'ILRU simulation 100,000 50% x 4,578,924 ops/sec ±1.40% (115 runs sampled)'
'LRU simulation 100,000 50% x 6,127,171 ops/sec ±1.66% (116 runs sampled)'
'TRC-C simulation 100,000 50% x 6,196,369 ops/sec ±1.74% (118 runs sampled)'
'TRC-L simulation 100,000 50% x 5,830,499 ops/sec ±1.68% (117 runs sampled)'
'DWC simulation 100,000 50% x 3,940,748 ops/sec ±1.49% (111 runs sampled)'
'Clock simulation 1,000,000 50% x 3,232,871 ops/sec ±3.00% (103 runs sampled)'
'ILRU simulation 1,000,000 50% x 1,750,395 ops/sec ±3.36% (108 runs sampled)'
'LRU simulation 1,000,000 50% x 2,225,422 ops/sec ±2.85% (107 runs sampled)'
'TRC-C simulation 1,000,000 50% x 2,205,121 ops/sec ±3.82% (104 runs sampled)'
'TRC-L simulation 1,000,000 50% x 2,131,169 ops/sec ±3.75% (108 runs sampled)'
'DWC simulation 1,000,000 50% x 2,021,860 ops/sec ±2.52% (104 runs sampled)'
'Clock simulation 100 90% x 17,288,235 ops/sec ±0.52% (122 runs sampled)'
'ILRU simulation 100 90% x 16,946,532 ops/sec ±0.61% (122 runs sampled)'
'LRU simulation 100 90% x 16,813,027 ops/sec ±0.44% (123 runs sampled)'
'TRC-C simulation 100 90% x 16,743,188 ops/sec ±0.50% (122 runs sampled)'
'TRC-L simulation 100 90% x 15,660,308 ops/sec ±0.54% (122 runs sampled)'
'DWC simulation 100 90% x 8,217,193 ops/sec ±0.44% (123 runs sampled)'
'Clock simulation 1,000 90% x 16,339,056 ops/sec ±0.65% (122 runs sampled)'
'ILRU simulation 1,000 90% x 14,831,917 ops/sec ±0.47% (121 runs sampled)'
'LRU simulation 1,000 90% x 14,862,361 ops/sec ±0.49% (121 runs sampled)'
'TRC-C simulation 1,000 90% x 14,763,737 ops/sec ±0.46% (123 runs sampled)'
'TRC-L simulation 1,000 90% x 13,862,219 ops/sec ±0.51% (122 runs sampled)'
'DWC simulation 1,000 90% x 8,416,098 ops/sec ±0.28% (123 runs sampled)'
'Clock simulation 10,000 90% x 14,564,733 ops/sec ±0.99% (121 runs sampled)'
'ILRU simulation 10,000 90% x 12,088,973 ops/sec ±0.47% (123 runs sampled)'
'LRU simulation 10,000 90% x 10,769,829 ops/sec ±0.51% (121 runs sampled)'
'TRC-C simulation 10,000 90% x 10,224,531 ops/sec ±1.03% (121 runs sampled)'
'TRC-L simulation 10,000 90% x 9,631,180 ops/sec ±0.45% (122 runs sampled)'
'DWC simulation 10,000 90% x 7,088,806 ops/sec ±0.43% (122 runs sampled)'
'Clock simulation 100,000 90% x 9,458,259 ops/sec ±1.16% (116 runs sampled)'
'ILRU simulation 100,000 90% x 7,171,011 ops/sec ±1.13% (116 runs sampled)'
'LRU simulation 100,000 90% x 7,224,473 ops/sec ±1.77% (117 runs sampled)'
'TRC-C simulation 100,000 90% x 7,129,766 ops/sec ±2.34% (113 runs sampled)'
'TRC-L simulation 100,000 90% x 6,765,188 ops/sec ±2.00% (112 runs sampled)'
'DWC simulation 100,000 90% x 5,446,218 ops/sec ±1.50% (116 runs sampled)'
'Clock simulation 1,000,000 90% x 4,329,004 ops/sec ±3.49% (104 runs sampled)'
'ILRU simulation 1,000,000 90% x 2,584,893 ops/sec ±2.23% (108 runs sampled)'
'LRU simulation 1,000,000 90% x 2,273,790 ops/sec ±1.98% (113 runs sampled)'
'TRC-C simulation 1,000,000 90% x 2,038,671 ops/sec ±2.55% (108 runs sampled)'
'TRC-L simulation 1,000,000 90% x 2,102,533 ops/sec ±2.35% (111 runs sampled)'
'DWC simulation 1,000,000 90% x 1,857,414 ops/sec ±1.93% (113 runs sampled)'
'ILRU simulation 100 90% expire x 4,268,085 ops/sec ±2.74% (116 runs sampled)'
'DWC simulation 100 90% expire x 7,095,161 ops/sec ±1.17% (119 runs sampled)'
'ILRU simulation 1,000 90% expire x 4,039,560 ops/sec ±3.60% (117 runs sampled)'
'DWC simulation 1,000 90% expire x 7,278,554 ops/sec ±0.37% (120 runs sampled)'
'ILRU simulation 10,000 90% expire x 3,515,365 ops/sec ±1.99% (117 runs sampled)'
'DWC simulation 10,000 90% expire x 5,470,851 ops/sec ±0.88% (121 runs sampled)'
'ILRU simulation 100,000 90% expire x 2,720,179 ops/sec ±2.12% (107 runs sampled)'
'DWC simulation 100,000 90% expire x 3,303,021 ops/sec ±2.23% (105 runs sampled)'
'ILRU simulation 1,000,000 90% expire x 1,404,398 ops/sec ±1.94% (111 runs sampled)'
'DWC simulation 1,000,000 90% expire x 1,464,143 ops/sec ±1.60% (115 runs sampled)'
export class TLRU<K, V> {
constructor(capacity: number, step?: number, window?: number, retrial?: boolean);
readonly length: number;
readonly size: number;
add(key: K, value: V): boolean;
set(key: K, value: V): this;
get(key: K): V | undefined;
has(key: K): boolean;
delete(key: K): boolean;
clear(): void;
[Symbol.iterator](): Iterator<[K, V], undefined, undefined>;
}